【Thorough Explanation】Newest Trends of Next-Gen Semiconductor Packages, Materials, and Substrates

Newest Trends of Next-Gen Semiconductor Packages, Materials, and Substrates


As the volume of information increases with the widespread use of the Internet of Things (IoT), 5G and other high-speed communication technologies, advanced driver-assistance systems (ADAS), and generative artificial intelligence (AI), information processing devices for data centers and terminals require the capability to transmit information more quickly in larger volumes and wider bandwidths. Accordingly, these devices require transistors and circuits more finely pitched and three-dimensionally integrated on silicon wafers in the semiconductor front-end process, while the demand rises for more advanced back-end process (packaging) technologies capable of enlarging substrates to accommodate larger, more densely packed, highly integrated chips. It is also important to deal with transmission loss and heat generation arising from increases in operating frequencies and information processing volumes.

With the semiconductor front-end process said to be reaching its physical and economic limits in the pursuit of finer-pitched circuits printed on wafers and larger semiconductor chips, attention is now focused on higher functionality, integration, and density using back-end assembly technologies.

This article describes the challenges and technological trends of cutting-edge next-generation semiconductor packages currently under development for 3D packages, along with the underlying technologies, materials, and substrates.

Growing importance of PKG technologies in the back-end process

Market and technology trends of semiconductor packages

Semiconductor package market trends

Telecommunications traffic is growing at an incredible pace with the continued development of future information societies envisioned with such initiatives as Germany’s “Industrie 4.0,” US General Electric’s Industrial Internet, and “Society 5.0” proposed by Japan as well as the spread of IoT, 5G and other high-speed networks, ADAS, and generative AI in our everyday lives. Data centers are also processing a rapidly increasing volume of information. Flip chip-ball grid arrays (FC-BGA) currently serve as the mainstream packages used for information processing devices in data centers, and are expected to see their quantities expand in the years ahead.

The image and chart below show the applications of semiconductor packages and their market growth forecast. To respond to the expected explosive growth in information processing and transmission, data centers, communication modules, and edge terminals must be equipped with semiconductor devices capable of processing information more speedily in larger volumes and wider bandwidths.

Applications of semiconductor packages

Applications of semiconductor PKG

Forecast of package market growth

The FC-BGA market is expected to grow.

forecast of PKGmarket growth(2020)

  Total :$10 Bn


forecast of PKGmarket growth(2025)

Total :$16Bn

  • Source:Prismark

From FC-BGA to next-generation packages

It is well known that FC-BGA packages significantly increase the number of signal input/output terminals compared with conventional SOP (small outline package) and QFP (quad flat package). However, FC-BGAs mount a semiconductor chip on each package substrate, with information between chips transmitted via the motherboard, as illustrated in the figure below.

On the other hand, 2.xD packages feature multiple semiconductor chips mounted on an interposer in a single package. In this package, information between chips is transmitted via the interposer, which is a sub-substrate used to connect chips with different functions through circuit line and connect them to package substrates with through-hole electrodes. A silicon (Si) interposer enables a larger amount of wiring and higher information transmission speed. The details are described later.

The practical application of 2.xD packages is underway as a leading candidate for next-generation package technologies that shorten the distance between chips and reduce signal processing loss compared with FC-BGA, thereby speeding up information transmission.

From FC-BGA to next-generation packages

Technology roadmap of next-generation packages

The figure below shows a rough roadmap of back-end process and packaging technologies with the aim of developing next-generation packages and the background which is the trends of communication networks and front-end process technologies.

Technology roadmap of next-generation packages

Underlying technologies required of next-generation packages and technology trends

The underlying technologies required of next-generation packages and the technology trends of higher integration, higher speed packaging technologies are described in detail below.

In the field of memory, the high bandwidth memory (HBM) standard has been put into practical use to increase information transmission speed, namely bandwidth, and to integrate more chips with memory chips stacked using through-silicon via (TSV) technology. An interface (I/F) chip with a processor is placed at the bottom of a standard four-layer memory, with these five chips interconnected by TSVs that require vertical, fine-pitch connection accuracy.

In the HBM standard, the stacked memory is connected to the processor by an Si interposer, which is a substrate used to conduct front and rear circuits with through-hole electrodes. First, both processor and memory are connected to the interposer (sub-substrate), and then the entire interposer is connected to the substrate. The Si interposer enables a far larger amount of wiring than ordinary substrates, and provides higher information transmission speed due to its excellent electrical conductivity.

It is common to combine processors and memories, and the technology of arranging in parallel, connecting, and packaging multiple semiconductor chips using interposers is referred to as 2.xD (dimensional) packaging. An increasing number of chips are expected to be mounted in 2.xD packages in the pursuit of higher integration and information transmission speed.

Chiplet technology is being applied more and more as a packaging method using interposers. To improve the yields of large-scale single-integrated chip circuits, chips are split into multiple smaller chips, or chiplets, and mounted on interposers to scale-up the circuits before being integrated into single packages. Combining processors with other chips can also help create a variety of specifications. These chiplet combinations represent one of the growing trends of higher integration and transmission speed.

In terms of the technology for interconnecting semiconductor chips to printed wiring substrates, fan-out wafer-level packaging (FOWLP) is now used for application processors and other devices to connect with packages larger than the area of semiconductor chips. Redistribution layers (RDL) are formed on semiconductor wafers using wafer-level chip scale package (WLCSP) technology that forms wiring in a wafer state with semiconductor front-end process technology, thereby fanning out the terminals outside the chip area. RDL fabrication requires technologies for accurately embedding RDLs without distorting the surface flatness.Please refer to the article ,“Positive photosensitive insulating resin for FOWLP RDL with high resolution and NMP-free新規ウィンドウで開く.”

As a package in the wireless communication field, a radio frequency front-end (RFFE) module integrating a power amplifier, high-frequency filter, RF switch, and low-noise amplifier is commonly used for a terminal’s remote radio head (RRH: device transmitting and receiving radio signals). The antenna-in-package (AiP) integrating these modules with antennas is also being considered.

In these ways, next-generation semiconductor packages are progressing toward higher integration and speed through heterogeneous integration with different types of chips modularized and integrated into single packages.

Amid these trends, development is underway to further advance 2.xD packaging to create 3D packaging technology for stacking and packaging multiple semiconductor chips, including memories and processors, in a three-dimensional direction, and even to combine 3D packages with three-dimensional integrated circuits (3DIC).

Trends overview

Underlying technologies required of next-generation packages

2.xD and 3D packages

With semiconductor packaging shifting from the current FC-BGA to the next-generation 2.xD and 3D packages, the primary purpose of heterogeneous integration is to increase the bandwidth (speed) of internal chip interconnection and achieve higher integration. While chips and wires are becoming finer with smaller terminal intervals, packages are expanding.

These trends are creating a challenging demand for materials used in next-generation packages. First, all materials require the capability to meet the challenges of transmission loss, heat generation, and stress at high frequencies. In addition, package substrates require larger areas, flatness, low warpage, and processability to support 3D packages.

Heterogeneous integration

Challenges and development trends of next-generation package materials

Challenges of 2.xD and 3D package materials

The requirements for materials used in 2.xD and 3D packages can be described as follows:

  • Encapsulants require low warpage (low CTE (coefficient of thermal expansion)) and high heat dissipation (high thermal conductivity).
  • Redistribution layers need the capabilities to form fine via holes, reduce loss, and control film thickness.
  • Core materials for package substrates require low warpage (low CTE), low loss, fine via hole formation, and film thickness control.
  • Heat resistance of thermal conductive sheets must be lowered
  • Underfills are required to provide low viscosity and high heat dissipation (high thermal conductivity)
  • Solder resists need the capabilities to form fine via holes and resist cracks.
  • Motherboard core materials require low warpage (low CTE), low loss, and flatness.

The substrate core materials are described in detail in section 4.

The biggest challenge is to minimize warpage of the entire package in each manufacturing process by combining components with different CTEs.

Performance required of 2.xD and 3D package materials

Roadmap and development status of 2.xD and 3D package materials

"The roadmap and development status of next-generation package materials新規ウィンドウで開く" shows the development status of JOINT2 .
Examples include fine bump formation 5 µm in diameter and 10 µm in pitch; underfilling properties when connecting bumps of this size; fluxless fine bump connections; RDL fine wiring formation with L/S = 1.5/1.5 µm; RDL multilayer fine wiring formation with 515 x 510 mm and L/S = 2.0/2.0 µm; chip-embedded 320 x 320 mm interposers; fabrication of large package substrates; interposer packaging; and secondary packaging on motherboards.

More information on JOINT2

Joint2 (Jisso Open Innovation Network of Tops 2) is a consortium of Resonac and 12 other companies involved in developing semiconductor packaging materials, substrates, and devices.


Challenges and development trends of next-generation package substrate core materials

Challenges of 2.xD and 3D packaging: substrate enlargement and warpage

The core material of printed wiring boards (substrates) for packages is comprised of electrically conductive copper foil, electrical insulating resin, fillers, and glass cloth supporting the packaging components.

CTE varies greatly among Si chips, substrate resins, and copper foils. Heating and cooling with different CTEs can cause such problems as substrate warpage, chip cracking, delamination in chip-to-package substrate connections, and connection failure between package substrates and motherboards. Next-generation packaging in particular requires substrates with smaller warpage, namely lower CTE, in response to narrower bump pitches and enlarged packages, or larger substrate areas.

Core material physical properties and substrate warpage simulation

Based on the FC-BGA structure shown in the figure below, we simulated the amount of warpage at 25°C (cooling) and 260°C (reflowing) for a flat substrate at 140°C (underfill (UF) curing temperature) while changing the CTE and elastic modulus of the core material.


The simulation results shown in the figure below, with the same color belts representing the same warpage amounts, reveal smaller substrate warpage with lower CTE and higher elastic modulus. The results also show that both lower CTE and higher elastic modulus are required to develop even lower warpage materials than Resonac’s relatively low-warpage W-705G (Type LH) among its conventional products.

Lower CTE core materials

The approximate CTE of a composite core material is expressed using the Schapery equation. This expression shows that a resin system’s (including fillers) CTE and elastic modulus must be lowered to reduce the core material’s CTE. As shown in the above simulation, higher elastic modulus is required for the entire core material to suppress substrate warpage, indicating the need to carefully balance lower elastic modulus for low CTE with higher elastic modulus for the entire core material.

Schapery equation(approx.CTE espression of a composite material)Schapery equation

Resonac uses its unique polymer blending technology to achieve both low elastic modulus for resin to lower a core material’s CTE and high elastic modulus for the entire core material. In other words, hard segments with a rigid backbone of planar stacking structures contribute to the core material’s lower CTE and higher elastic modulus, while soft segments with a flexible backbone of chain-like molecular structures help lower the core material’s CTE and suppress residual stress by lowering the resin’s elastic modulus. Each segment is optimally blended to realize both low CTE and high elastic modulus for the entire core material.

Properties required of core materials: lowering resin’s CTE

Latest low CTE cores (E-795G, E-795G (Type LH)) and TYPE-F core in pursuit of flatness and thickness accuracy

Please refer to The latest core materials for next-generation package substrates新規ウィンドウで開くfor details of newest core materials “E-795G and E-795G(Type LH)” and “TYPE-F”

  • “E-795G and E-795G(Type LH)” are created based on its development policies and ideas on suppressing warpage while providing both low CTE and high elastic modulus.
  • With or without “Type LH” refer to the difference of glass cloths.
  • “TYPE-F” is designed to achieve both flatness and higher thickness accuracy.

Both E-795G and E-795G (Type LH) achieve low CTE and high elastic modulus compared with our conventional E-705G, E-705G (Type LH), E-770G, and E-770G (Type LH). Resonac has successfully developed high- elastic modulus, low CTE core materials by optimally blending hard and soft segments to apply low CTE resins, as mentioned earlier, and by increasing the fill rate of fillers.

High thickness accuracy is required to ensure connection reliability during the packaging process. Component-embedded substrates especially require thickness accuracy for cores and components, with unevenly thin or thick cores likely to damage the components. Resonac’s TYPE-F, an upgraded version of E-705G and E-705G (Type LH), pursues both higher thickness accuracy and flatness using the same material.

As described above, next-generation semiconductor package substrates require larger areas to accommodate multiple devices and support future 2.xD and 3D packages, and their core materials need to provide low CTE and high elastic modulus to achieve low warpage as well as high thickness accuracy to ensure connection reliability during the packaging process.

In response to these demands, Resonac has developed the core material MCL-E-795G with low CTE and high elastic modulus by applying a low CTE resin and increasing the volume of fillers. MCL-E-795G reduces package warpage by 15%–20% compared with our conventional types. In addition, Resonac’s high thickness accuracy core material TYPE-F contributes to improved connection reliability of bump connections.

  • “MCL” is Resonac Corporation’s registered trademark in Japan, the United States, Italy, Canada, Singapore, France, Benelux, Poland, Malaysia, Mexico, South Korea, Hong Kong, Taiwan, and China.
  • TYPE-F   is Resonac Corporation’s registered trademark in Japan.

Author:Hideki Tomozawa
Release date: 14th December, 2023

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