Manufacturing Processes and Materials Used in Advanced Semiconductor Packaging

On a silicon wafer, an insulating layer such as an oxide film—serving as the base for the wiring layers—is formed using chemical vapor deposition (CVD). Next, blind vias for through-silicon vias (TSVs) are created by etching. After applying an insulating liner to the via walls, the vias are filled with copper plating. Redistribution layers (RDLs) are then built on both the front and back sides of the wafer. The wafer is thinned to expose the TSVs, and an additional RDL is formed on the backside. RDLs are wiring layers designed to reroute connections to match the chip’s I/O positions. Finally, pads for micro-bumps^※1 are formed on the top surface, completing the interposer. Photosensitive insulating films are used in the formation of RDLs.

Next, logic ICs and chiplets such as high bandwidth memory (HBM) are mounted on the interposer. Specifically, micro-bumps pre-formed on each chip’s connection pads are aligned with corresponding pads on the interposer and joined using flip-chip bonding technology. When stacking logic ICs, hybrid bonding or micro-bump technology is used for inter-chip connections.

After chip assembly, underfill material is dispensed into the gaps between the chips and the interposer by capillary action and then cured. Underfill is a polymer material that seals and reinforces the gap between the chip and the substrate, mitigating stress on solder bumps caused by thermal cycling. The entire chip area on the interposer is then encapsulated with an epoxy resin molding compound.

The interposer with mounted chips is then attached to an organic package substrate. The interposer and substrate are connected via solder balls on the underside of the interposer through processes such as reflow or thermal compression bonding (TCB). Underfill is again dispensed and cured into the gap between the interposer and the substrate. Finally, a thermal interface material (TIM) and heat spreader are attached to efficiently dissipate heat, completing the advanced semiconductor package. 
Materials used in package substrate manufacturing include copper-clad laminates^※2, CMP slurry^※3, photosensitive dry films^※4, and solder resist^※5.