The Evolution of Semiconductor Packaging

In the 1970s and 1980s, packages primarily served as a “case” to protect the chip and provide electrical connections to external circuits. During this period, lead-frame packages such as DIP (Dual In-line Package), SOP (Small Outline Package), and QFP (Quad Flat Package), which placed terminals around the periphery of the package, were the mainstream solution.

In the 1990s, as portable devices became smaller and faster, lead-frame packages began to face challenges such as terminal deformation and an increased risk of short circuits due to finer lead pitch. To address these issues, packages optimized for high-density mounting—such as BGA (Ball Grid Array) and CSP (Chip Size Package), which placed terminals on the bottom—gained popularity. At the same time, reducing interconnect length and improving thermal characteristics became critical.

In the 2000s, the trend toward multifunctional electronic devices, led by mobile phones, brought attention to the concept of SiP (System-in-Package), which integrates multiple functions within a single package. A key technology was Stacked CSP, where multiple chips were vertically stacked using staggered arrangements or spacers—primarily for memory—enabling smaller form factors and higher capacity. In the late 2000s, PoP (Package-on-Package) emerged, stacking memory on top of processors. This PoP structure maintained manufacturing yield while offering design flexibility and becoming indispensable for high-density implementations in smartphones. These advances transformed the package into a critical platform for system miniaturization and performance enhancement.

In the 2010s, increasing requirements for thinner profiles, higher performance, and lower power consumption drove rapid advances in semiconductor packaging. Innovations included fan-out technology, which redistributes chip terminals outward by wiring layers, and TSV (Through-Silicon Via), which connects stacked chips through the shortest possible path. High-density interconnects using micro-bumps also became practical. By the mid-2010s, the acceleration of supercomputing and deep learning research highlighted the von Neumann bottleneck, where data transfer speed between CPU and memory became a limiting factor. This rapidly spurred demand for wide-bandwidth connections between processors and large-capacity memory within the same package. The solution was 2.5D packaging that uses a silicon interposer for high-density connections. Initially limited to high-end applications, this technology—along with 3D packaging—has become indispensable for modern computing infrastructure, driven by the explosive growth of generative AI in the 2020s.