Resonac Launches R&D Center for Next-Gen Semiconductor Package Technology under U.S.-Japanese Consortium “US-JOINT”

- Public and private sector representatives from Japan and the U.S. gather for ceremony in Silicon Valley -

April 20, 2026
Resonac Holdings Corporation

Resonac Corporation today inaugurated a new R&D center to mark the full-scale launch of “US-JOINT,” a consortium of 12 Japanese and U.S. material and equipment manufacturers led by the company, with the goal of establishing new models for developing next-generation semiconductor-packaging technologies. To commemorate the occasion, a ceremony attended by government officials and participating companies from both countries was held at the consortium's newly operational base in Silicon Valley on April 20.

Opening Ceremony

The new R&D center is the first in the United States dedicated to developing advanced semiconductor-packaging technologies. Resonac and the consortium partners will leverage this R&D base in Silicon Valley to validate new concepts in collaboration with major users of advanced semiconductors. By capturing market needs in real time and combining the technological capabilities of leading Japanese and U.S. manufacturers of materials and equipment, the consortium will accelerate the research and development of materials, evaluation and packaging technologies to enable the rapid commercialization and deployment.

Hidehito Takahashi, President and CEO of Resonac, commented: "US-JOINT aims to shorten the proof-of-concept (PoC) period from approximately six months to as little as one month by enabling 12 participating Japanese and U.S. companies to conduct development in Silicon Valley, home to major hyperscalers. Through “collaboration” between semiconductor-related companies from Japan and the United States, the initiative will accelerate global semiconductor innovation."

Resonac will leverage US-JOINT's technological foundation and knowledge to play a central role in promoting co-creation while overseeing the consortium. As a materials manufacturer with a comprehensive understanding of the entire semiconductor manufacturing process, Resonac will bring together the technologies and ideas of participating companies to contribute to concept validation and accelerate co-creation targeted at market needs.

Dilip Vijay, Vice President and Head of Global IC Operations, Broadcom Inc., commented: "A collaborative effort like US-JOINT is exactly what the industry has needed. I am very much looking forward to the US-JOINT R&D center's full-scale operation in Silicon Valley. We expect this initiative to speed up semiconductor innovation and spark entirely new breakthroughs beyond what we see today."

Raja Swaminathan, Vice President of Heterogeneous Integration Technologies, Advanced Micro Devices, Inc., said: "With US-JOINT now fully operational in Silicon Valley, we expect face-to-face technical dialogue to lead to more efficient joint development through faster feedback and clearer understandings. We welcome US-JOINT’s efforts and look forward to the innovations and strengthened ecosystem collaboration this initiative can enable."

Kazumi Nishikawa, Director-General for Economic Security Policy, Trade and Economic Security Bureau, Ministry of Economy, Trade and Industry, remarked: “The expansion of generative AI and the current requirements of computing demands more advanced packaging. I am very confident that US-JOINT is just the start of innovation for advanced packaging and chiplets in generative AI computing. Finally, I truly appreciate the effort that led to today, and I hope that today's one step can lead to a tremendous outcome for the U.S. and Japan and to the world.”

 

Overview of US-JOINT

NameUS-JOINT (JOINT: Jisso Open Innovation Network of Tops)
ObjectivesTo create an evaluation platform for next-generation semiconductor packaging and develop packaging technology in the United States
Participants (alphabetical order)12 companies (as of April 20, 2026)
Resonac Corporation; Azimuth Industrial; KLA Corporation; Kulicke and Soffa Industries; MEC Co., Ltd.; Moses Lake Industries; Namics Corporation; TOKYO OHKA KOGYO CO., LTD.; Toppan Inc.; TOWA Corporation; ULVAC, Inc.; and 3M Company
LocationUnion City, California, USA
LaunchApril 2026 (full-scale operation)
Main Facilities/EnvironmentAdvanced semiconductor packaging processes (patterning, bonding, molding, plating, etc.), evaluation and analysis equipment, cleanrooms (Classes 100 and 1,000)
Facility RoleR&D center for validating next-generation semiconductor-packaging concepts
Intended UsersFabless companies, semiconductor manufacturers, and engineers from participating companies
US-JOINTロゴ

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